1. Field of the Invention
The present invention generally relates to wiring layout of a semiconductor device constituted by multi-layered wiring.
2. Description of the Related Art
An example of conventional multi-layered wiring of a semiconductor device is shown by FIGS. 5A–5D, which is designed by CAD (Computer Aided Design). As is well known, the multilayer is constituted by metal layers and via layers that are stacked one by one.
In the present specification, an n-th metal layer (n is a natural number), especially wiring thereof (metal portion) is expressed as “METALn layer”, and an n-th via layer, especially a hole portion thereof, is expressed as “VIAn layer”. As the number n increases, it signifies that the corresponding layer is positioned in the upper part of the semiconductor device.
Accordingly, connection between a METALn layer and a METALn+1 layer is established by hole means VIAn; connection between the METALn layer and an METALn−1 layer is established by hole means VIAn−1; connection between the METALn+1 layer and an METALn+2 layer is established by hole means VIAn+1; and so on.
With reference to FIGS. 5A–5D, a plan view of the METALn−1 layer, the METALn layer, and the VIAn−1 layer that connects the two metal layers is given at (a); a plan view of the METALn layer, METALn+1 layer, and the VIAn layer that connects the two metal layers is given at (b); and a plan view of the METALn+1 layer, the METALn+2 layer, and VIAn+1 layer that connects the two metal layers is given at (c). The structure shown by (c) is placed on the structure shown by (b) that is placed on the structure shown by (a). For easy reference, FIG. 7 provides a legend.
In FIGS. 5A–5D, a cross-sectional view of the device constituted by the structures shown at 5C, 5B, and 5A taken along a plane R is shown at 5D. Further, FIG. 6 is an enlargement of an approximately central part of the section enclosed by a single-dot chain-line shown at FIG. 5D.
According to the conventional example shown by FIGS. 5A–5D, a design rule is that the minimum value of the “width” of a wiring track and a hole in each layer is set to be the “interval” between wiring tracks and holes. That is, as indicated at FIG. 5A, the distance shown by “b” is the minimum value of the design rule. In FIGS. 5A–5D, all the wiring tracks and the holes are laid out with the minimum value width and at the minimum value intervals. In this manner, wiring in a metal layer is usually arranged using the minimum value width and the minimum value interval of the holes and the wiring tracks as far as possible.
However, in a layer material known as Low-K, and in a miniaturization process employing a Cu wiring process, a problem of a short circuit between VIAs occurring exists.
For example, in a process of dual damascene, the VIAn−1 layer and the METALn layer are simultaneously formed; the VIAn layer and the METALn+1 layer are simultaneously formed; and so on. Here, at places indicated by S and T of FIG. 6, peeling of the layer material often occurs due to imperfection of adhesion of the materials at the boundary region between the VIAn−1 layer and the METALn−1 layer, at the boundary region between the VIAn layer and the METALn layer, and so on. Peeling becomes remarkable with a film material of a low dielectric constant like the layer material known as Low-K. Further, since lower layers are exposed to heat stress a greater number of times than upper layers, the lower layers tend to have peeling.
In addition, in the case of a Cu wiring process, after a Cu layer is seeded in a damascene slot of dual damascene, the Cu layer is grown up, and Cu is embedded by a kind of plating means. At this time, Cu often permeates to a place where peeling takes place, given that Cu has a higher permeability than other conventional wiring materials such as Al. Consequently, the possibility exists that a short circuit will occur at the places S and T of FIG. 6.
Patent reference 1 (below) discloses a layout of a semiconductor integrated circuit employing a mesh-wiring power supply structure, wherein cross-talk is taken into consideration. According to the patent reference 1, the power supply mesh is forcibly provided at intervals of 2 widths of the wire in the perpendicular and the horizontal priority wiring directions such that signal wires are shielded. Accordingly, the interval between VIAs measures two widths of the VIA, and this is effective to prevent a short circuit from occurring between the VIAs. However, the double-width wiring interval definitely decreases density of the signal wires.
[Patent Reference 1]
JP, 2001-127162, A